This section introduces aspects that may help facilitate a better understanding of the invention. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art.
Digital media (e.g., digital audio, image and video) have become an integral part of our daily life. Increasingly high speed digital signal processors and computers, and sophisticated coding techniques (e.g., MP3, JPEG, MPEG2, etc.) lend great support to the proliferation of use of digital media. Analog-to-digital signal converters (ADCs) are essential for transforming the analog media we perceive to the digital media to take advantage of the advanced digital technology. As people demand higher and higher digital quality, traditional electronic ADCs no longer can afford the desired bandwidth and resolution in certain digital applications, e.g., digital communications, where a sampling rate on the order of ten giga-Hertz (GHz) is required. For example, in K. Pulton et al., “A 20 GS/s 8b ADC with a IMB Memory in 0.18 μm CMOS,” IEEE ISSCC 2003/Session 18/Nyquist A/D Converters/Paper 18.1, 2003, an electronic ADC is described whose sampling rate is 20 GHz. However, such an ADC can only afford a reasonable bit resolution within 1 GHz input bandwidth, which no longer is sufficient for many latest digital applications. Because of the bandwidth and resolution limitations imposed by use of electronic ADCs, the industry lately has turned its focus on using photonics in ADCs to attempt to overcome such limitations.
FIG. 1 illustrates a typical generic photonic ADC 100, connected to external sources. As shown in FIG. 1, analog signal source 103 provides an analog signal to be digitized by ADC 100. The latter includes a conventional opto-electric track and holder amplifier (THA) 105, which is configured to sample the analog signal from source 103. Radio frequency (RF) oscillator 108 generates a sequence of electrical pulses at a predetermined frequency (fs), which may be on the order of 10 GHz. This sequence of pulses is used to drive mode lock laser (MLL) 111 of a conventional design to generate an optical clock signal of the corresponding frequency. Such an optical clock signal is fed via an optic waveguide 113 (shown using a hatched line to differentiate it from an electric waveguide shown using a solid line) to opto-electric THA 105 to drive its sampling clock. The analog signal samples from THA 105 are distributed amongst N conventional sub-ADCs denoted 119-1, 119-2 . . . , and 119-N, respectively, where N is a predetermined number. These N sub-ADCs, which may be electronic ADCs of well known design, are connected at the output of THA 105 in a “fan-out” arrangement. In a conventional manner, the magnitudes or values of the samples are expressed in electrical voltage. Dictated by clock signals (not shown), which are derived from that of RF oscillator 108 and which have a frequency of fs/N and different clock phases from one another, the sub-ADCs take in samples from THA 105 in a time-interleaved manner each at a rate of fs/N. The N sub-ADCs individually quantize the values of the clocked-in samples, and code the quantized sample values in binary bits, which are provided at the output of the sub-ADCs. Each sub-ADC may also sub-sample the clocked-in samples before its quantization process. Multiplexer 123 multiplexes the resulting binary bits from the N sub-ADCs to provide a bit sequence representing the digitized version of the analog signal input to ADC 100.